1. Field of the Invention
The present invention generally relates to a first-in, first-out memory circuit, more particularly, to a first-in, first-out memory circuit using a dual port random access memory.
This application is a counterpart of Japanese patent application, Serial Number 115378/1998, filed Apr. 24, 1998, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
A conventional first-in, first-out memory circuit (hereinafter FIFO memory) using a dual port RAM is shown in FIG. 21. The conventional FIFO memory 500 is mainly made up of a dual port RAM 510, a write address counter 520 (an address counter for writing data), a read address counter 530 (an address counter for reading data), a coincidence detect circuit 540.
The dual port RAM 510 has a data write terminal 510W for receiving a data write signal WR, a write address terminal 510WA for receiving a write address signal, a data input port 510I for inputting data, a data read terminal 510R for receiving a data read signal RD, a read address terminal 510RA for receiving a read address signal, and a data output port 510O for outputting data.
The write address counter 520 has a clock input terminal 520CL which receives the data write signal NVR. The write address counter 520 outputs the write address signal to the write address terminal 510WA of the dual port RAM 510 and an input terminal 540I1 of the coincidence detect circuit 540. An explanation of the coincidence detect circuit 540 is provided later.
The read address counter 530 has a clock input terminal 530CL which receives the data read signal RD. The read address counter 530 outputs the read address signal to the read address terminal 510RA of the dual port RAM 510 and an input terminal 540I2 of the coincidence detect circuit 540.
The coincidence detect circuit 540 has a clock input terminal 540CL1 which receives the data write signal WR and a clock input terminal 540CL2 which receives the data read signal RD. The coincidence detect circuit 540 recognizes the state of the dual port RAM 510 according to the data write signal WR, the data read signal RD, the write address signal and the read address signal and outputs a FUL signal or a EMP signal. The FUL signal and the EMP signal will be explained later.
Next, an operation of the FIFO memory circuit 500 will be explained hereinafter with reference to FIG. 22 and FIG. 23.
FIG. 22 is a timing chart showing an operation of the FIFO memory 500. FIG. 23 is a flow diagram indicating data storing states of the dual port RAM 510. As illustrated in FIG. 22, the dual port RAM 510 has eight addresses therein.
First, when the data write signal WR (data write pulse) is not transferred to the FIFO memory 500 and the data write signal WVR is in an L level, the write address counter 520 does not count. Thus, no data are written into the dual port RAM 510 at this time. Thereafter, when the data write signal WR is transferred to the FIFO memory 500, the data can be written into the addresses of the dual port RAM 510 as indicated by the write address counter 520. Whenever writing the data into the dual port RAM 510 is executed, the address in which the write address counter 520 indicates is increased by one. (Refer to from time t0 to time t1 shown in FIG. 23)
When eight data write pulses NVR are inputted to the FIFO memory 500 while the data read signal RD (data read pulse) is never inputted once to them, the data are written into all addresses in the dual port RAM 510. (The circle in FIG. 23 indicates that the data is written into or stored in the corresponding addresses.) At this state, it is necessary to execute a predetermined operation so that the data can not be written any more into the dual port RAM 510. In order to carry out that operation, the coincidence detect circuit 540 outputs the FUL signal having an H level when the address signal output from the write address counter 520 coincides with the address signal output from the read address counter 530. (Refer to from time t1 shown in FIG. 23)
After that, when the data read pulse RD is transferred to the FIFO memory 500, the data stored in the address of the dual port RAM 510 as indicated by the read address counter 530 can be read out. In the case that the stored data is read out from this vacant address, this address where the stored data has been stored becomes vacant. Therefore, it is possible to write new data into this address again. The coincidence detect circuit 540 outputs the FUL signal having the L level when the address signal output from the Write address counter 520 does not coincide with the address signal output from the read address counter 530. (Refer to from time t2 shown in FIG. 23)
Reading out the data is enabled by applying the data read pulse RD to the FIFO memory 500. The data located at the address indicated by the read address counter 530 can be read out. Whenever reading out the data from the dual port RAM 510 is executed, the address indicated by the read address counter 530 is increased by one. (Refer to from time t2 to time t3 in FIG. 23)
When eight data read pulses RD are inputted to the FIFO memory 500 while the data write pulse WR is never applied once to them, the data are read out from all addresses in the dual port RAM 510. At this state, it is necessary to execute a predetermined operation so that the data can not be read out any more from the dual port RAM 510. In order to carry out this operation, the coincidence detect circuit 540 outputs the EMP signal having the H level when the address signal output from the read address counter 530 coincides with the address signal output from the write address counter 520. (Refer to time t3 shown in FIG. 23)
After that, when the data write pulse WR is transferred to the FIFO memory 500, the data can be written into the address where the write address counter 520 indicates. When the data is written into this address, it is possible to read out the data from this address again. The coincidence detect circuit 540 outputs the EMP signal having the L level when the address signal output from the read address counter 530 does not coincide with the address signal output from the write address counter 520. (Refer to time t4 shown in FIG. 23)
The conventional FIFO memory can treat a single kind of data such as data comprised of 8 bits. However, it is difficult to deal with two or more kinds of data.
The conventional FIFO memory can handle a data interface dealing with a single channel, however, it is difficult to change the specification thereof in order to handle a data interface dealing with multiple channels.
Consequently, there has been a need for an improved FIFO memory circuit.